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This article mainly builds a data processing platform for a multi-physiological parameter measurement system, embedding a 32-bit Nios II soft core processor in the FPGA, which is used to control the transmission, storage and display of data. Mainly completed the customization of this data processing platform hardware system and wrote corresponding programs to control the data collection, storage and display.
Designed with the Nios II processor as the core, all interface circuits can be integrated on the same FPGA with a simple structure. At the same time, taking advantage of the Nios II soft core's online configuration, changing the internal structure of the FPGA through software programming can quickly and easily achieve system performance expansion and upgrade, greatly shortening the system development cycle and improving cost performance.
Overall design of multi-physiological parameter measurement system
A complete physiological parameter detection system structure can be divided into three parts: front-end detection circuit, interface part, and data processing platform, which respectively complete physiological signal collection, transmission, and signal processing functions.
The front-end detection circuit mainly completes signal collection and quantization. By connecting different sensors, different physiological signals can be collected, including common physiological signals such as ECG signals, pulse signals, and body temperature. After some amplification, filtering and analog-to-digital conversion processing, the collected physiological signals are sent to the data processing module for processing through the serial port to obtain various physiological parameters needed, and finally displayed or wirelessly transmitted. This article mainly completes the construction of data processing platform based on FPGA technology.
Design of Data Processing Platform Based on FPGA Technology
This design builds a data processing platform with Nios II soft core processor as the core. It first controls the serial port to receive data and stores it in the corresponding storage space. After related data processing, the corresponding waveforms and corresponding waveforms are displayed by controlling the display peripherals. parameter. Nios II is a RISC universal embedded processor soft core based on Harvard architecture, which can be combined with user logic and programmed into Altera's FPGA. The processor has a 32-bit instruction set, a 32-bit data channel and configurable instructions and data buffer [2-3].
Construction of the hardware platform
In this design, the Nios II soft core processor is used as the control core, which forms a basic data processing platform by connecting serial ports, storage devices, and display peripherals. Therefore, the hardware platform shown in Figure 2 was built.
The hardware platform is mainly implemented on Terasic's Altera DE2 development board. The main components of the system are the Nios II core, on-chip memory, timer, VGA controller, LCD controller, etc., all integrated on an Altera Cyclone II FPGA chip , Use SoPC Builder to configure and generate the system on chip. SoPC Builder automatically generates HDL files for each module, and automatically generates some necessary arbitration logic to coordinate the work of various components in the system [4].
Customization of Niosâ…¡ soft core system
According to the hardware platform constructed in Figure 2, use SoPC Builder to customize the 32-bit Niosâ…¡ CPU and the parameterized Avalon interface bus, and then add the necessary component cores in the platform to adapt to the needs of Niosâ…¡ system functions. Generate as shown in Figure 3 Basic customization shown.
software design
The software part mainly controls the reception, storage and display of data. In the custom IP core module, you can design some data processing algorithms, such as digital filtering algorithms and the calculation of certain physiological parameter values, including blood pressure and heart rate.
Design of data receiving module
This design uses a serial port to receive data. The UART serial port module used in Nios II development is a SoPC Builder component, which is included in the Nios II development kit. Some data structures about UART and commonly used UART functions are also pre-defined in the development kit, so that the UART can be easily programmed.
First, set the parameters of the UART in SoPC Builder, including the baud rate and the format of the transmitted data frame. When the hardware design of the system is completed under SOPC Builder, a hardware abstraction layer (HAL) file is automatically generated as the interface between the software and the hardware, and the relevant data structure of the UART module is declared in the excalibur.h header file. The software accesses the hardware through the abstract address mapping interface of the peripheral. This design uses serial interrupt to receive data, and its process is shown in Figure 4.
Design of data display module
In the Nios II system, VGA is a peripheral IP core. The most important part of the design is the generation of VGA timing, which is the key to normal output display and is included in the VGA controller. The VGA controller is generated by the interface to user logic in SoPC Builder. First, a timing output and RGB signal output module are defined in the hardware description language. The dot clock 25.175MHz is generated by the clock provided by the development board through frequency division of the phase-locked loop. The phase-locked loop is added to the system through the MegWizard tool. This module implements the dot clock, composite synchronization control signal, composite blanking control signal, line synchronization and field synchronization signal required for VGA output; it also completes reading the output display command and color value from the register. The dot clock, composite synchronization control signal, composite blanking control signal and RGB digital signal are input to the ADV7123, and line synchronization, field synchronization and the RGB analog signal converted and output by the ADV7123 are input to the VGA display. In addition, the hardware description language must also be used to read and write registers to make the VGA controller port comply with the Avalon interface specification.
The timing control of VGA module and the output program of RGB signal are written in HDL language. The timing simulation results are shown in Figure 5.
Design of data storage module
The development board used in this design provides a wealth of storage resources, including 8MB of SDRAM, 512KB of SRAM, and 4MB of Flash, as well as an SD card interface, and a general-purpose GPIO interface can also be easily connected to an extended memory chip.
This paper mainly designs the data processing platform with Nios II soft core processor as the core. In the future design, the algorithm of data processing can be further studied, including digital filtering of signals and numerical calculation of parameters.
The data processing platform based on the extremely flexible Nios II processor can be quickly configured and upgraded by selecting different front-end data acquisition modules and corresponding data processing algorithms according to the needs of different hospitals, communities and families. At the same time, it can be connected through the network to achieve telemedicine and information sharing. The use of field programmable gate arrays in the design of modern medical instruments will significantly shorten the development cycle, reduce design risks, reduce costs, improve product reliability and flexibility, and achieve modularity and miniaturization.
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