Main features and block diagram of FM4 S6E2C series

Cypress's FM4 S6E2C family is a highly integrated 32-bit MCU based on ARM® Cortex®-M4 with integrated flash and SRAM, as well as motor control timer, ADC and communication interface (USB, CAN, UART, CSIO (SPI) , I2C, LIN) peripherals, as well as hardware encryption engine (AES-128/192/256, SHA-256, PKA). Operating frequency 200MHz. This article introduces the main features and block diagram of FM4 S6E2C series, development board FM4-216- ETHERNE main features and block diagrams, circuit diagrams and PCB design drawings.

Devices in the S6E2CC Series are highly integrated 32-bit microcontrollers with high performance and compeTITIve cost. This series is based on the ARM Cortex-M4F processor with on-chip flash memory and SRAM. The serieshasperipherals such as motor control TImers, A/Dconverters, And communicates to the TYPE3-M4 product categories "FM4 Family Peripheral Manual Main Part (002-04856)."

The FM4 S6E2C-Series provides a highly integrated single chip solution with 200MHz of CPU power, up to 2Mbytes of dual banked high speed on chip flash memory, up to 256Kbytes of on chip SRAM, and integrated peripheral features including IEEE1588 compliant 10/100 base Ethernet, CAN, CAN-FD, USB and inverter control timers. The dedicated hardware cryptographic engine (AES-128/192/256, SHA-256, PKA) enables secure data communication with minimal CPU processing overhead.

Main features of FM4 S6E2C series:

32-bit ARM Cortex-M4F Core

 Processor version: r0p1

 Up to 200 MHz frequency operation

 FPU built-in

 Support DSP instructions

Memory protection unit (MPU): improves the reliability of an embedded system

 Integrated nested vectored interrupt controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels

 24-bit system timer (Sys Tick): system timer for OS task management

On-chip Memories

 Flash memory

Thisseries isbased on two independent on-chip flashmemories.

 Up to2048 Kbytes

 Built-in flashaccelerator system with 16 Kbytes trace buffer memory

 Read access to flashmemorythatcan be achieved without wait-cycle up to an operatingfrequency of 72 MHz. Even at the operating frequency more than 72 MHz, an equivalent single cycle access to flashmemorycan be obtained by the flashaccelerator system.

 Security function for code protection

 SRAM

This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connectedto the I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to system bus ofCortex-M4F core.

 SRAM0: up to 192 Kbytes

 SRAM1: 32 Kbytes

 SRAM2: 32 Kbytes

External Bus Interface

 Supports SRAM, NOR, NAND flashand SDRAM device

 Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)

 8-/16-/32-bit data width

 Up to 25-bit address bus

 Supports address/data multiplexing

 Supports external RDY function

 Supports scramble function

 Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units.

 Possible to set two kinds of the scramble key

USB Interface (Max two channels)

The USB interface is composed of a function and a host.

 USB function

 USB2.0 Full-speedsupported

 Max 6 EndPoint supported

• EndPoint 0 is control transfer

• EndPoint 1, 2 can be selected bulk-transfer, interrupt-transfer or isochronous-transfer

• EndPoint 3 to 5 can select bulk-transfer or interrupt-transfer

• EndPoint 1 to 5 including double buffer

• The size of each endpoint is as follows.

−Endpoint0, 2to 5: 64byte

• EndPoint 1: 256byte

USB host

 USB2.0 Full-Speed/Low-Speedsupported

 Bulk-transfer, interrupt-transfer, and isochronous-transfer support

 USB Device connected/dis-connected automatically detect

 IN/OUT token handshake packet automatically

 Max 256-byte packetlength supported

 Wake-up function supported

CAN Interface (Max twochannels)

 Compatible with CAN specification 2.0A/B

 Maximum transfer rate: 1 Mbps

 Built-in 32-message buffer

CAN-FDInterface (Onechannel)

 Compatible with CAN Specification 2.0A/B

 Maximum transfer rate: 5Mbps

 Message buffer for receiver: up to 192 messages

 Messagebuffer for transmitter: up to 32messages

 CAN with flexible data rate(non-ISO CAN FD)

 Notes:

 CAN FD can communicate between non-ISO CAN FD and ISO CAN FD, because non-ISO CAN FD and ISO CAN FD are different frame format.

 About the problem of “non-ISO CAN FD”, see the White Paper from CiA (CAN in Automation).

Multi-function Serial Interface (Max16Channels)

 Separate 64 byte receive and transmit FIFObuffers for channels 0 to 7.

 Operation mode is selectable for each channel from the following:

 UART

 CSIO (SPI)

 LIN

 I2C

 UART

 Full-duplex double buffer

 Selection with or without parity supported

 Built-in dedicated baud rate generator

 External clock available as a serial clock

 Various error detect functions available (parity errors, framing errors, and overrun errors)

 CSIO (SPI)

 Full-duplex double buffer

 Built-in dedicated baud rate generator

 Overrun error detect function available

 Serial chip select function (ch 6 and ch 7 only)

 Supports high-speed SPI (ch 4 and ch 6 only)

 Data length 5 to 16-bit

 LIN

 LIN protocol Rev.2.1 supported

 Full-duplex double buffer

 Master/slave mode supported

 LINbreak field generation (can change to 13-to 16-bit length)

 LINbreak delimiter generation (can change to 1-to 4-bit length)

 Various error detect functions available (parity errors, framing errors, and overrun errors)

 I2C

 Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) supported

 Fast mode Plus (Fm+) (Max 1000 kbps, only for ch 3= ch A and ch 7=ch B) supported

DMA Controller (EightChannels)

DMA controller has an independent bus, so the CPU and DMA controller can process

Simultaneous

 Eightindependently configured and operated channels

 Transfer can be started by software or request from the built-in peripherals

 Transfer address area: 32-bit (4 GB)

 Transfer mode: Block transfer/Burst transfer/Demand transfer

 Transfer data type: bytes/half-word/word

 Transfer block count: 1 to 16

 Number of transfers: 1 to 65536

DSTC (Descriptor System Data Transfer Controller; 256 channels)

The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the descriptor system and, following the specified contents of the descriptor thathas already been constructed on thememory, can access directly the memory/peripheral device and perform the data-transfer Operation.

It supports the software activation, the hardware activation and the chain activation functions.

A/DConverter (Max 32 Channels)

 12-bit A/D Converter

 Successive approximation type

 Built-in threeunits

 Conversion time: 0.5μs at5V

 Priority conversion available (priority at two levels)

 Scanning conversion mode

 Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for priority conversion: 4steps)

D/A Converter (Maxtwochannels)

 R-2R type

 12-bit resolution

Base Timer (Max 16channels)

Operation mode is selectedfrom the following for each channel:

 16-bit PWM timer

 16-bit PPG timer

 16-/32-bit reload timer

 16-/32-bit PWC timer

General Purpose I/O Port

This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals; moreover, the port relocate function is built in. It can set the I/O port to which the peripheral functioncan be allocated.

 Capable of pull-up control per pin

 Capable of reading pin level directly

 Built-in port-relocate function

 Up to 120high-speedgeneral-purpose I/O ports in 144-pin package

 Some pins 5V tolerant I/O.See “4. Pin Descriptions” and “5. I/O Circuit Type” for the corresponding pins.

Multi-function Timer (Max threeunits)

The multi-function timer is composed of the following blocks:

Minimum resolution: 5.00ns

 16-bit free-run timer × 3 ch/unit

 Input capture × 4 ch/unit

 Output compare × 6ch/unit

 A/D activation compare × 6ch/unit

 Waveform generator × 3 ch/unit

 16-bit PPG timer × 3 ch/unit

The following functionscan be used to achieve the motor control:

 PWM signal output function

 DC chopper waveform output function

 Dead time function

 Input capture function

 A/D convertor activate function

DT DTIF (motor emergency stop) interrupt function

Real-Time Clock (RTC)

The real-time clock can count year, month, day, hour, minute, second, or day of the week from 01 to 99.

Interrupt function with specified date and time (year/month/day/hour/minute/second/day of theweek) is available. This function is also available by specifying only year, month, day, hour, or minute.

 Timer interrupt function after set time or each set time.

 Capable of rewriting the time with continuing the time count.

 Leap year automatic count is available.

Quadrature Position/Revolution Counter (QPRC; Max fourchannels)

The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the positionencoder. It is also possible to use up/down counter.

Detection The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.

 16-bit position counter

 16-bit revolution counter

 Two 16-bit compare registers

Dual Timer (32-/16-bit Down Counter)

The dual timer consists of two programmable 32-/16-bit down counters.Operation mode is selectable from the following for each channel:

 Free-running

 Periodic (= Reload)

 Oneshot

Watch Counter

The watch counter is used for wake up from low-power consumption mode. It is possible to select the main clock, sub clock, built-in High-speed CR clock, or built-in low-speed CR clock as the clock source.

 Interval timer: up to 64 s (max) with a sub clock of 32.768 kHz

External Interrupt Controller Unit

 External interrupt input pin: Max 32pins

Include Include one non-maskable interrupt (NMI)

Watchdog Timer (Twochannels)

A watchdog timer can generate interrupts or a reset when a time-out value is reached.

This series consists of two different watchdogs:a “hardware” watchdog and a “software” watchdog.

The hardware watchdog timer is clocked by low-speed internal CR oscillator. The hardware watchdog is thus active in any power saving mode except RTC mode and Stopmode.

Cyclic Redundancy Check (CRC) Accelerator

The CRC accelerator helps to verify data transmission or storage integrity.

CCITT CRC16 and IEEE-802.3 CRC32 are supported.

 CCITT CRC16 generator polynomial: 0x1021

 IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7

Programmable Cyclic Redundancy Check (PRGCRC) Accelerator

The CRC accelerator helps a verify data transmission or storage integrity.

CCITT CRC16, IEEE-802.3 CRC32and generating polynomial are supported.

 CCITT CRC16 generator polynomial: 0x1021

 IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7

 Generating polynomial

SD Card Interface

It is possible to use the SD card that conforms to the following standards.

 Part 1 Physical Layer Specification version 3.01

 Part E1 SDIO Specification version 3.00

 Part A2 SD Host Controller Standard Specification version 3.00

 1-bit or 4-bit data bus

Ethernet-MAC

 Compliant with IEEE802.3 specification

 10Mbps/100 Mbps data transfer rates supported

 MII/RMII for external PHY device supported.

 MII: Max one channel

 RMII: Max one channel

 Full-duplex and half-duplex mode supported.

 Wake-ON-LAN supported

 Built-in dedicated descriptor-system DMAC

 Built-in 2Kbytestransmit FIFO and 2Kbytesreceive FIFO.

 Compliant IEEE1558-2008 (PTP)

I2S (Inter-IC Sound Bus) Interface (TX x onechannel, RX x onechannel)

 Supportsthree transfer protocols

 I2S

 Left justified

 DSP mode

 Separate clock generation block for flexible system integration options

 Master/slave mode selectable

 RX Only, TX Only or TX and RX simultaneous operation selectable

 Word length is programmable from 7-bits to 32-bits

 RX/TX FIFO integrated (RX: 66 words x 32-bits, TX: 66 words x 32-bits)

DMA DMA, interrupts, or polling based data transfer supported

High-speed Quad SPI

Up to 66 MHz clock rates for very fast data transfers to and from SPI compatible devices.

Up to 256 Mbytes of memory mapped address space.

 Single data rate (SDR)

 Supportssingle,dual,and quad data modes

 Built-indirectmode and commandsequencermode

 Direct mode: Accessby use oftransmissionFIFO/reception FIFO(up to16word x 32bit)

 Commandsequencer mode: Automaticaccessassignedtoexternaldevice area.

Clock and Reset

 Clocks

Five clock sources (twoexternal oscillators, twointernal CR oscillators, and Main PLL) that are dynamicallyselectable.

 Main clock: 4MHz to 48MHz

 Sub clock: 30 kHz to 100 kHz

 High-speed internal CR clock: 4MHz

 Low-speed internal CR clock: 100kHz

 Main PLL Clock

 Resets

 Reset requests from INITX pin

 Power on reset

 Software reset

 Watchdog timer reset

 Low-voltage detector reset

 Clock supervisor reset

Clock Supervisor (CSV)

Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.

 External OSC clock failure (clock stop) is detected, reset is asserted.

 External OSCfrequency anomaly is detected, interrupt or reset is asserted.

Low-Voltage Detector (LVD)

This series includes two-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, the low-voltage detector functiongenerates an interrupt or reset.

LV LVD1: error reporting via interrupt

LV LVD2: auto-reset operation

Low-power consumption mode

Six lowpower consumption modes are supported.

 Sleep

 Timer

 RTC

 Stop

 Deep standby RTC (selectable from with/without RAM retention)

 Deep standby stop (selectable from with/without RAM retention)

Peripheral Clock Gating

The system canreducethe current consumption of the total system with gating the operation clocks of peripheral functionss not used.

VBAT

The consumption power during the RTC operation can be reduced by the power supply independent from the RTC (calendar circuit) / 32 kHz oscillation circuit. The following circuits can also beused.

 RTC

 32-kHz oscillation circuit

 Power-on circuit

 Back up register: 32 bytes

 Portcircuit

Crypto Assist Function

These features are enabled for the crypto assist function. The dedicated middleware is necessary for this calculator operation.

 PKA (Public Key Accelerator)

 PKA (Public Key Accelerator) is modular exponentiation calculation accelerator used of RSA Public Key crypto and so on.

 Available bit length: Up to 2048-bit

 AES calculator

 AES (Advanced Encryption Standard) calculator is a AES common key crypto accelerator which is compliant with FIPS (Federal Information Processing Standard Publication) 197.

 Available key length: 128/192/256-bit

 CBC modeand ECB mode support

 SHA-256 calculator

 SHA-256 calculator is a SHA-256 hash function accelerator which is compliant with FIPS180-2.

 External Bus Data Scramble

 It enables to scramble input/output data of External Bus Interface.

Voice Function

These features are enabled for the voice function. Thededicated library is necessary for using the voice function.

 Automatic Speech Recognition (ASR)

 100 custom commands in multiple languages

 User is defined with a text file (no audio input or training required)

 Natural Language Understanding (NLU)

Debug

 Serial wire JTAG debug port (SWJ-DP)

 Embedded trace macrocells (ETM) provide comprehensive debug and trace facilities.

AH AHB trace macrocells(HTM)

Unique ID

Unique value of the device (41-bit) is set.

Power Supply

 Five power supplies

 Wide range voltage: VCC= 2.7Vto 5.5V

 Power supply for USB ch 0 I/O: USBVCC0= 3.0V to 3.6V (when USB is used)

= 2.7V to 5.5V (when GPIO is used)

 Power supply for USB ch 1 I/O: USBVCC1= 3.0V to 3.6V (when USB is used)

= 2.7V to 5.5V (when GPIO is used)

 Power supply for Ethernet-MAC I/O: ETHVCC = 3.0Vto 5.5V(when Ethernet is used.)

= 2.7Vto 5.5V(when GPIO is used)

 Power supply for VBAT: VBAT= 1.65Vto 5.5V

Figure 1. FM4 S6E2C Series Block Diagram

Development Board FM4-216-ETHERNE

The FM4-216-ETHERNET is a development platform for developing applications using the ARM® Cortex®-M4-based FM4 S6E2CC MCU. This board provides a variety of peripherals for evaluating different modules of the MCU, including Ethernet, CAN and USB Host .

Figure 2. Development board FM4-216-ETHERNE outline drawing

Figure 3. Main function distribution map of development board FM4-216-ETHERNE

Figure 4. Main features and block diagram of the development board FM4-216-ETHERNE

Figure 5. Development board FM4-216-ETHERNE circuit diagram (1)

Figure 6. Development board FM4-216-ETHERNE circuit diagram (2)

Figure 7. Development board FM4-216-ETHERNE circuit diagram (3)

Figure 8. Development board FM4-216-ETHERNE circuit diagram (4)

Figure 9. Development board FM4-216-ETHERNE circuit diagram (5)

Figure 10. Development board FM4-216-ETHERNE circuit diagram (6)

Figure 11. Development board FM4-216-ETHERNE circuit diagram (7)

Figure 12. Development board FM4-216-ETHERNE PCB design (1)

Figure 13. Development board FM4-216-ETHERNE PCB design (2)

Figure 14. Development board FM4-216-ETHERNE PCB design (3)

Figure 15. Development board FM4-216-ETHERNE PCB design (4)

Figure 16. Development board FM4-216-ETHERNE PCB design (5)

Figure 17. Development board FM4-216-ETHERNE PCB design (6)

Figure 18. Development board FM4-216-ETHERNE PCB design (7)

Figure 19. Development board FM4-216-ETHERNE PCB design (8)

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